Programmable logic devices (PLDs) are popular general purpose logic devices. PLDs generally include an AND array, an OR array and an input/output (I/O) macrocell. A routing interconnect is used to transport signals to various elements within the device. The AND array typically includes a plurality of logical AND gates and generates a large number of output signals called AND or product terms. The AND terms are received by the OR array which generally includes a plurality of OR gates. The OR array generates a number of output signals, called sum terms, by ORing selected AND terms together. The sum terms generated by the OR array are then received by the I/O macrocell which comprises a number of circuit elements including D-type data registers. The I/O macrocell of most PLDs outputs signals from the PLD and also feeds output signals back into the AND array for further use.
Many families of programmable logic devices such as PLDs, complex PLDs (so-called CPLDs), field programmable gate arrays (FPGAs) and application specific integrated circuits (ASICs) are synchronously clocked devices. That is, these families of devices have dedicated pins which receive a system clock signal for use within the programmable logic device. For example, some conventional synchronous programmable logic devices receive clock input signals from dedicated clock/input pins and route such signals to programmable registers within one or more I/O macrocells.
Other families of PLDs can accommodate asynchronous clocking wherein the clock signals which are used to capture data in registers contained in these devices are created by logically combining a number of logic inputs and/or internally generated logic signals to create the clock signal. In these devices, a particular signal generated, for example, by the AND or OR arrays can be utilized, in place of a dedicated system clock, to capture a signal in one of the register elements in an I/O macrocell. This function is termed asynchronous clocking because a signal other than a dedicated system clock is utilized by one or more register elements. Where the asynchronous clock signal is generated by the AND array, the asynchronous clock signal may be referred to as a product term clock signal. Where the asynchronous clock signal is generated by the OR array, it may be referred to as a sum term or a sum of products term if the asynchronous clock signal is generated by a combination of signals provided by the AND and OR arrays.
In architectures where an asynchronous signal is used by one or more register elements in an I/O macrocell as a clock signal, these logically derived clocks signals are restricted to very low frequencies of operation because the asynchronous signals usually must traverse the large general purpose logic array of the CPLD or FPGA. As a result, an input change in the incoming signal(s) from which the logic derived clock signal is created must wait for any preceeding transitions to transit the slow logic array signal path before the subsequent input transitions can be processed. This restriction limits the frequency at which these devices can operate to frequencies much lower than those possible for synchronous operation in which external clock signals are applied directly to a register clock input via fast, dedicated clock signal paths.
In addition, the input signals from which the logic derived clock signal is created can arrive at unpredictable times at the programmable device. The unpredictable signal arrival time may result in a violation in the setup or hold time relative to the data signal to be captured in the register. The difference between logic derived clock signal and data signal transit times through the programmable device can be considerable. Therefore, to ensure that this potential mismatch in signal timing does not cause a violation of the data signal setup time or hold time relative to the logic derived clock signal input to the register, operation must be derated to allow for the worst case difference or skew between the data signal and the logic derived clock signals which can be anticipated in a given CPLD or FPGA due to variations in internal logic placement and routing.
FIG. 1 shows an example of product terms used to create logic derived clock signals in macrocells of a CPLD which are part of a larger logic array of one of the logic blocks of a CPLD. CPLD 10 includes macrocells 12 and logic block logic array 14. Logic block logic array 14 receives a number of signals 16 from a programmable interconnect matrix (PIM) within CPLD 10. The PIM (not shown) acts as a user programmable routing matrix for signals within the device. Signals 16 from the PIM are passed to logic block logic array 14 for routing to one or more macrocells 12. Note that, in general, signals 16 from the PIM include the logic complement of each signal. Thus, for "n" signals, 2n signal lines are present in logic block logic array 14. Likewise, each of the logic gates 18 in logic block logic array will have 2n input lines. For clarity, however, only one input line for each logic gate 18 is shown and this shorthand form of notation is typically employed and understood by those skilled in the art and is used in this application to illustrate exemplary embodiments of the present invention.
One or more of the signals 16 provided to logic block logic array 14 may be combined using dedicated logic gates 19 to produce a product term clock signal 20. Product term clock signal 20 may be used as a logic derived clock signal by a register 22 within one of the macrocells 12. In general, register 22 captures data signals presented on line 29 in response to a rising (or falling) edge of a clock signal (CLK) on clock line 25. Using a multiplexer 24 within macrocell 12, a user can select between product term clock signal 20 or a synchronous clock signal 26 as the means by which data signals can be captured in register 22. Data signals which are captured in register 22 may ultimately be provided to an output pad 28 and/or routed back through logic block logic array 14 or the PIM to form more complex signal combinations.
The product term clock signal 20 shown in FIG. 1 may be responsive to one or more external input signals which can arrive at CPLD 10 at any time from an external system. There is significant risk that these external signals will produce changes at the clock signal input of register 22 which will violate required setup and hold times relative to the data signal supplied on line 29 for capture by register 22. Such an occurrence can cause the wrong data state to be captured by register 22. Also, when setup and hold times are violated there is significant probability that a metastable event can occur which will cause an undesired logic state to be output by register 22 until the metastable event has been resolved. Even though the correct output logic state may eventually be obtained, the time required for recovery from the metastable condition can be much longer than the usual clock input to valid data output delay. Normally, additional margins must be added to the logic derived clock signal period to allow for the resolution of such metastable states. This requirement adds even more delay to the logic derived clock period, lowering the frequency of operation even further.
Also as shown in FIG. 1, if a "sum" expression is required to generate the product term clock signal 20, it must be created in another macrocell 12 and fed back to the input of the clock product term 19. This added pass through logic block logic array 14 reduces even further the possible frequency of operation of the product term clock signal 20.
FIG. 2 shows the generation of logic derived clock signals in the logic cells of an FPGA by routing an output of one logic cell to the clock input of a register which receives data from an output of another logic cell. An input signal change which produces a change in the logic derived clock signal can be several logic blocks prior to the clock input of the controlled register.
FPGA 30 may include several logic cells 32a-32d. Logic cell 32a may receive and operate on one or more signals provided from a PIM 34. As illustrated, logic cell 32a receives three input signals 35. The circled interconnections of the inputs 35 within PIM 34 represent programmable elements (e.g., fuses, antifuses, flash cells, RAM cell controlled pass transistors, etc.) which have been programmed so as to route the respective signals to logic cell 32a.
Logic cell 32a may perform one or more operations on the input signals 35 and provide an output signal 36 to PIM 34. This output signal 36 may be one of several input signals 37 to logic cell 32b which performs other operations and produces output signal 38 to PIM 34. Finally, signal 38 may be one of several inputs 39 to logic cell 32c which performs further logical operations and provides data signal 40 to register 41.
Register 41 captures data signal 40 on the rising edge of a logic derived clock signal 42 which is itself received from PIM 34. Logic derived clock signal 42 is produced by logic cell 32d from a number of input signals 43. These input signals 43 may themselves be routed through PIM 34 from other logic cells prior to reaching logic cell 32d. If any of the input signals 43 which are used to create the logic derived clock signal 42 are derived from external asynchronous input signals whose transitions cannot be reliably predicted, no timing precautions will guarantee proper observance of relative data and clock signal timing requirements at the register 48 input.
It should be noted that the transit times for data signals and clock signals are strongly affected by the relative internal locations of the signal sources since FPGAs typically exhibit a wide distribution of internal interconnect delays. Consequently, the relative signal timing of the logic derived clock signal and the data signal is difficult to predict and designs which rely on logic derived clock signals cannot be guaranteed to function reliably. As a result of this timing unpredictability, some FPGAs provide a clock enable which can be used to wait for all the transit delays to occur before enabling the clock signal path to the logic cell register. This approach still requires a delay to be observed to accommodate the worst case possible delay in the clock signal path and the data signal must be held at the data input of the register to allow for this worst case delayed clock enable. This scheme results in very slow performance with logic derived clock signals.
Any logic derived clock signal (e.g., product term clock signal 20 in FIG. 1 or signal 42 in FIG. 2) whose arrival at a controlled register (e.g., register 22 in FIG. 1 or register 41 in FIG. 2) can result in the violation of setup or hold timing relative to the data signal input (e.g., signal 29 in FIG. 1 or signal 40 in FIG. 2) can generate a metastable register state which will frequently require a time longer than a normal clock signal to valid data output delay time to resolve to a stable output state. In the event that the arrival of a logic derived clock signal cannot be predicted, additional timing margins must be provided in the clock signal path to allow for the metastable recovery time to ensure an acceptably low level of probability of a functional failure due to a metastablity event.
Accordingly, what is desired is a means to provide fast logic generated clock signals for use in CPLDs, FPGAs and other programmable devices to allow higher performance logic derived clock frequencies. It is also desirable to have a means for synchronizing the logic derived clock signals to the data so as to eliminate the risk of register data signal and clock signal timing mismatches and to reduce or eliminate the potential for metastability-induced functional failures. Further, it is desirable that the logic HIGH interval of the synchronized logic derived clock signal be of fixed duration for variable duration logic HIGH intervals of the input logic signal from which the logic derived clock signal will be created. Such a fixed duration logic HIGH interval of the synchronized logic derived clock signal will provide a predictable clock duty cycle within the programmable device.